1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same, and more particularly to a semiconductor device that includes transistors and to a method of manufacturing the same.
2. Description of Related Art
Miniaturization of semiconductor devices is now under a rapid progress. And in order to catch up with this progress, miniaturization of transistors used in those semiconductor devices is also accelerated. Furthermore, along with the progress of such miniaturization of those semiconductor devices and transistors, the dimensional accuracy required for their manufacturing processes is getting more and more strict. However, it is still difficult to prevent dimensional variation among such transistors to be caused by their manufacturing processes while it is required that those transistors are formed very accurately in desired sizes.
Under such circumstances, JP-A-Hei 7-263677 discloses a technique for obtaining a MOS transistor that includes minute gate electrodes manufactured very accurately. FIG. 1A through 1D are cross sectional views of the semiconductor device disclosed in JP-A-Hei 7-263677 with respect to its manufacturing method. At first, as shown in FIG. 1A, an insulation film pattern 311 is formed in a predetermined region partitioned by an element isolation layer 305 on a semiconductor substrate 301. After this, as shown in FIG. 1B, a gate insulation film 309 is formed all over the semiconductor device 301 so as to cover the insulation film pattern 311, then a conductive film 308b is formed all over the gate insulation film 309. In FIG. 1B, the gate insulation film 309 formed on the insulation film pattern 311 and the insulation film pattern 311 merge into one, so the insulation film 309 is omitted here as a separate label. Then, as shown in FIG. 1C, the conductive film 308b is etched back in an anisotropic process to form a gate electrode 308 at the side wall of the insulation film pattern 311; the side wall remains as is. After this, as shown in FIG. 1D, the gate insulation film 309 and the insulation film pattern 311 except for the portion under the gate electrode 308 are removed by etching. Then, a source-drain region (not shown) is formed at both sides of the gate electrode 308.
As a related technique, JP-A-2000-210736 discloses another semiconductor device. This semiconductor device includes SRAM cells, each of which includes a first drive transistor, a second drive transistor, a first passage transistor, a second passage transistor, a third passage transistor, and a fourth passage transistor. The first drive transistor constitutes an n-conductivity type first inverter. The second drive transistor has an input terminal and an output terminal that are connected to the output terminal and the input terminal of the first inverter respectively to form a second inverter. The second drive transistor is n-conductivity type. The first passage transistor is provided in a route between the output terminal of the first inverter and the first bit line. The second passage transistor is provided in a route between the output terminal of the second inverter and the second bit line. The third passage transistor is provided in a route between the first passage transistor and the first bit line. The fourth passage transistor is provided in a route between the second passage transistor and the second bit line. And each drive transistor and each passage transistor are equal in gate width or in gate length.